1. Field of the Invention
The present invention relates to a solid state image sensor comprising a number of pixels each of which is formed by a lateral type static induction transistor in which a source-drain current passes in parallel with a surface of a semiconductor substrate.
2. Related Art Statement
The solid state image sensor of the kind mentioned above has been proposed in U.S. patent applications Ser. Nos. 556,347 and 715,641. FIG. 1A is an equivalent circuit of the lateral type static induction transistor (LSIT), the structure of which is shown in FIG. 1B, developed by the applicant to which the present application has been asigned. This LSIT is of n-channel type and constitutes a common source configuration. A source terminal 1 is connected to a source electrode (S) and a source voltage V.sub.S is applied thereto. A drain terminal 2 is coupled with a drain electrode (D) via a load resistor (R.sub.L)4 and the drain electrode is connected to an output terminal 5 deriving an output voltage V.sub.OUT. A drain voltage V.sub.D is applied to the drain terminal 2. A gate terminal 3 is connected to a gate electrode (G)6 and a gate voltage V.sub.G is applied thereto. Incident light 7 is made incident upon the gate electrode 6. Further a substrate voltage V.sub.SUB is applied to a substrate terminal 8.
In FIG. 1B, 21 is an n type silicon substrate, 22 is an n.sup.- type epitaxial layer formed on the substrate 21, 23 is an n.sup.+ source region diffused in the surface of the epitaxial layer 22 and 24 is an n.sup.+ drain region which is also diffused in the surface of the epitaxial layer 22, the n.sup.- epitaxial layer 22 forming a channel region. Further, 25 is a buried gate region which is formed on the substrate 21 (and beneath the channel region 22) as a p.sup.+ buried layer and 26 is a p.sup.+ type surface gate region diffused in the surface of the channel region 22 between the source and drain regions. Both gate regions 25 and 26 store the signal charges generated in the channel region 22 in response to the optical input and are interconnected by means of a p.sup.+ diffused region 27 to form signal charge storage regions which control the potential barrier in the channel between the source and the drain from both sides by the static induction effect of the gate voltage thereon. On the p.sup.+ regions 26 and 28 there is provided an insulating film 29 such as SiO.sub.2 etc., on which film is provided an electrode 30 to form an MIS type gate electrode. Finally, 31 is an isolation region for isolating the lateral SITs from each other, each SIT comprising a source region 23, a drain region 24 and signal charge storage regions 25, 26, 27 and 28.
FIGS. 2A to 2D are signal waveforms for explaining the operation of LSIT shown in FIGS. 1A and 1B. FIG. 2A illustrates the gate voltage V.sub.G applied to the gate terminal 3, FIG. 2B the drain voltage V.sub.D applied to the drain terminal 2, FIG. 2C the source voltage V.sub.S applied to the source terminal 1 and FIG. 2D depicts the substrate voltage V.sub.SUB applied to the substrate terminal 8. One operational period is assumed to be T which is consisting of store period T.sub.1, readout period T.sub.2 and reset period T.sub.3. During the whole operation period T, the source voltage V.sub.S is maintained at the ground voltage V.sub.S1 (V.sub.S1 =0) and the substrate voltage V.sub.SUB is remained at the reverse bias voltage V.sub.SUB1 (V.sub.SUB1 &lt;0). During the store period T.sub.1, the gate voltage V.sub.G is set to a deep reverse bias voltage V.sub.G1 (V.sub.G1 &lt;0) and holes induced at an interface between the semiconductor portion immediately below the gate and a gate insulating film in accordance with the incident light 7 are stored. It should be noted that during the store period T.sub.1, the drain voltage V.sub.D is set to the ground voltage V.sub.D1. Next, in the readout period T.sub.2 the gate voltage V.sub.G is changed to a gate readout voltage V.sub.G2 (V.sub.G1 .ltoreq.V.sub.G2 &lt;0), and the drain voltage V.sub.D is changed to a readout voltage V.sub.D2 (V.sub.D2 &gt;0). In this manner, an output signal proportional to an amount of the incident light is readout. Then, in the reset period T.sub.3, the gate voltage V.sub.G is changed to a forward bias voltage V.sub.G3 (V.sub.G3 &gt;0), and the holes stored under the gate are flowed away. It should be noted that during the reset period T.sub.3, the drain voltage V.sub.D may be set to the readout voltage V.sub.D2 as shown in FIG. 2B or may be set to the ground voltage V.sub.D1.
FIG. 3 is a graph showing an output characteristic of LSIT illustrated in FIGS. 1A and 1B, i.e. a relation between an amount of light incident upon the gate and the output voltage V.sub.OUT readout at the output terminal 5. In FIG. 3, when an amount of light l is zero, the LSIT is in an OFF state and the output voltage V.sub.OUT is equal to the drain voltage V.sub.D. When the incident light becomes stronger, the LSIT becomes more conductive and the output voltage V.sub.OUT is decreased accordingly. When the incident light exceeds a saturation amount l.sub.1, the output voltage becomes equal to a constant value V.sub.OUT1. In a range from the zero to the saturation value l.sub.1, it has been experimentally confirmed that the output voltage V.sub.OUT is in proportion to an amount of the incident light (V.sub.OUT .varies.l).
In the solid state image sensor comprising the above explained LSITs, LSITs each constituting respective pixels are arranged in matrix and are raster-scanned to derive an image signal. There have been proposed three scanning methods, i.e. drain-gate selection method, source-gate selection method and source-drain selection method.
FIG. 4 is a circuit diagram showing a solid state image sensor in which LSITs are arranged in matrix and are raster-scanned by the drain-gate selection method. In this embodiment, m.times.n LSITs 150-11, 150-12 . . . 150-21, 150-22 . . . 150-mn are arranged in m.times.n matrix and are successively readout by the XY address system. Each LSIT forming a pixel may comprise a gate region surrounding at least one of source and drain regions or situating between the source and drain regions. Source terminals of all LSITs are commonly connected to the ground potential and gate terminals of LSITs in each rows arranged in the X direction are connected to respective row lines 151-1, 151-2 . . . 151-m. Drain terminals of LSITs in each columns arranged in the Y direction are connected to respective column lines 152-1, 152-2 . . . 152-n which are commonly connected to video line 154 and ground line 154' via column selection transistors 153-1, 153-2 . . . 153-n and anti-selection transistors 153-1', 153-2' . . . 153-n', respectively. The video line 154 is connected to a video voltage source V.sub.DD through a load resistor 155. The row lines 151-1, 151-2 . . . 151-m are connected to a vertical scanning circuit 156 and receive vertical scanning signals .phi..sub.G1, .phi..sub.G2 . . . .phi..sub.Gm, respectively. Gate terminals of the column selection transistors 153-1, 153-2 . . . 153-n and anti-selection transistors 153-1', 153-2' . . . 153-n' are connected to a horizontal scanning circuit 157 and receive horizontal scanning signals .phi..sub.D1, .phi..sub.D2 . . . .phi..sub.Dn and their inverted signals, respectively.
Now the operation of the solid state image sensor shown in FIG. 4 will be explained with reference to waveforms shown in FIGS. 5A to 5F showing vertical and horizontal scanning signals .phi..sub.G and .phi..sub.D. Each of the signals .phi..sub.G1, .phi..sub.G2 . . . applied to the row ines 151-1, 151-2 . . . assumes a readout gate voltage V.sub..phi.G having a small amplitude and a reset gate voltage V.sub..phi.R having a large amplitude. During a scanning period t.sub.H of one row, the signal .phi..sub.G assumes the value V.sub..phi.G and during a horizontal blanking period t.sub.BL, it assumes the value V.sub..phi.R. The horizontal scanning signals .phi..sub.D1, .phi..sub.D2 . . . are used to select the column lines 152-1, 152-2 . . . and assume a low level by means of which the column selection transistors 153-1, 153-2 . . . 153-n are made conductive and the anti-selection transistors 153-1', 153-2' . . . 153-n' are made non-conductive.
Due to the operation of the vertical scanning circuit 156, when the signal .phi..sub.G1 is changed to V.sub..phi.G, an LSIT group 150-11, 150-12 . . . 150-1n is selected and when the horizontal selection transistors 153-1, 153-2 . . . 153-n are successively made conductive by the signals .phi..sub.D1, .phi..sub.D2 . . . .phi..sub.Dn supplied from the horizontal scanning circuit 157, the image signals are successively readout on the video line 154 from LSITs 150-11, 150-12 . . . 150-1n. These LSITs 150-11, 150-12 . . . 150-1n are simultaneously reset when the signal .phi..sub.G1 is changed to the high level V.sub..phi.R to prepare for a next light signal accumulation. When the signal .phi..sub.G2 is changed to the value V.sub..phi.G, a next LSIT group 150-21, 150-22 . . . 150-2n connected to the row line 151-2 are selected and the image signals are successively readout from these LSITs 150-21, 150-22 . . . 150-2n by means of the horizontal scanning signals .phi..sub.D1, .phi..sub.D2 . . . .phi..sub.Dn. Then these LSITs are simultaneously reset when the signal .phi..sub.G2 is changed to V.sub..phi.R. In the manner explained above, successive LSITs are readout to derive a video signal of one field.
In the solid state image sensor mentioned above, the drains of LSITs which are not selected are fixed to the ground potential by means of the anti-selection transistors, and thus photocarriers induced by the incident light are advantageously stored during the photocarrier storing period. However, this solid state image sensor has the following disadvantages.
Generally, the signal readout of the solid state image sensor as well as an image pick-up tube is processed in a signal processing circuit and is subjected to a .gamma.-correction in which a white clip is effected at a level larger than a standard signal by about 1.1 times, said standard signal being equal to a tenth of a saturation level. Therefore, when considering a whole image pick-up system including the signal processing circuit a dynamic range of the output signal is substantially narrower than that of the solid state image sensor or image pick-up tube. This results in that when an object to be picked-up has a strong contrast, dark portions are uniformly made dark and bright portions are emphasized to a greater extent. In this manner, the solid state image sensor comprising LSITs has a drawback that it has a too large .gamma. value.
In the solid state image sensor mentioned above, LSIT has gate voltage V.sub.G -drain current I.sub.D characteristic shown in FIG. 6. It is now assumed that under such an incident light condition that the output signal is just saturated when the signal readout is effected at the gate voltage V.sub.2, the drain current I.sub.D becomes substantially zero at the gate voltage of V.sub.1. When LSIT 150-11 is to be read out, the vertical scanning signal .phi..sub.G1 becomes equal to V.sub.2 and a signal current flows through LSIT 150-11 in accordance with the incident light condition. In LSITs 150-21, 150-31 . . . 150-m1, all the vertical scanning signals .phi..sub.G2, .phi..sub.G3 . . . .phi..sub.Gm are equal to V.sub.1 and any currents do not flow through source-drain paths of these LSITs. In this manner only LSIT 150-11 is selected and read out. However, if LSIT 150-21 is under an excessive incident light condition, a drain current flows through this LSIT 150-21 even through the vertical scanning signal .phi..sub.G2 is equal to V.sub. 2. Therefore, when LSIT 150-11 is to be read out, LSIT 150-21 connected to the same column line 150-1 as LSIT 150-11 is erroneously read out. In this manner when an amount of incident light is excessive, an erroneous signal is introduced from non-selected pixels and it is not possible to effect a normal image pick-up operation.